One of the major problems in integrated circuit design is the ability to adequately test the final IC design. This problem increases with increasing complexity of the integrated circuit chip.
Recently, megamodules have been used in the design of application-specific integrated circuits (ASICs). Each of these megamodules, which for example may be RAMS, ROMS, universal asynchronous receiver-transmitters (UARTs), programmable logic arrays or other logic circuits, are usually defined as integrated circuit modules of at least a 500-gate complexity. These megamodules may be predesigned and stored in a library. The megamodules can then be used in the design of an ASIC by placing the design within a certain area on the IC chip.
Conventionally, these megamodules are available as standard catalog devices and are designed without testability. In order to test the ASIC, a custom test program must be developed for that particular chip. Because a custom testing program has to be devised for each custom chip, the costs associated therewith are less than optimum.
More recently, peripheral cells have been provided for input and output during normal operation of the chip, and also for inputting and outputting testing signals of a testing program. These peripheral cells are typically of input, output and input/output types. Testing programs have been previously devised that use input cells for the input test terminals and output cells for the output test terminals. This has the disadvantage of restricting the number of test pins of any type to the number of available signal pins of the same type. A need has therefore arisen for a more flexible testing method and apparatus such that any signal pin of the ASIC chip may be used for any megamodule testing program.